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Wafers with photoresist drying in wet process technology research

Author: DuanHaiDong
Tutor: HuangYiPing；LuoShiZhou
School: Fudan University
Course: Electronics and Communication Engineering
Keywords: Wet Etch Wet Clean Wafer Dry PR Peeling Native Oxide
CLC: TN405
Type: Master's thesis
Year: 2011
Downloads: 20
Quote: 0
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Abstract

With scaling down of transistor, the requirement of cleaning on wafer surface is getting critical. It makes wet process i.e wet etch and wet cleaning are considered more and more important process in semiconductor manufacturing. Drying is the last step in wet process, which may enormously influence production yield. Therefore, a new challenging is brought into wet process and drying technology,In this thesis, dual gate wet etch and salicide block wet etch process will be regarded as a research object in 0.13μm logic technology, which the wafers surface have been covered with photoresist. And we studied the defects like PR peeling, native oxide and surface particles after wet process. With defects observation in different metrology equipment like KLA surface scan, OM(Optical Microscope), SEM(Scanning Electron Microscope) etc, we found the defects element and regularity of distribution.Via certain experiments in various drying conditions including IPA temperature, flow rate and wafer lifting speed, we found the correlation between the defects and the drying conditions. From the research, it indicated PR peeling was free from the drying step in the condition of IPA temperature below 40℃. The water mark and surface particles will be slighter with lowering of wafer lifting speed and increasing of IPA flow rate, temperature. Furthermore, the conditions including PR type, HMDS time and Hard Bake temperature in ligthogrophy process will affect the PR status in wet etching process.After the experiments, we analyzed the results to carry out the final solution. The PR surface wafer should be dried in room temperature, IPA flow rate can be set 25L/min. And considering the capacity of manufacture, the wafer lifting speed was seperated two steps(the upper wafer section was set lmm/s and the lower was 0.5mm/s). As a result of inline implementation, the wafers die yield can be improved 8%. In additon, some defects rework methods and its die yield comparaiton were also introduced for your reference.With growing attentions in environmental pollution and resources regeneration, we gave some foresee in wet process and drying technology at the end.

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