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GaAs heterojunction and a high electron mobility transistor technology to improve the yield of the device

Author: YinYing
Tutor: HongZhiLiang；NieChunLei
School: Fudan University
Course: IC Engineering
Keywords: HBT pHEMT Failure Analysis Interconnect Lift-off Yield Enhancement
CLC: TN405
Type: Master's thesis
Year: 2011
Downloads: 100
Quote: 0
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Abstract


GaAs MMIC is widely applicated in high frequency、high speed、large power field. The main processes are:Hetero-junction Bipolar Transistor (HBT)、pseudomorphic High Electron Mobility Transistor (pHEMT) and Metal-semiconductor FET (MESFET). GaAs material and GaAs devices have the overwhelming advantage that silicon technology is difficult to surpass the performance in the field of high frequency and large power application. However the special physical and chemical characteristics of GaAs material together with its different process from silicon makes GaAs devices R&D costs much higher compared with silicon. The poor process repeatability、uniformity and higher proportion of yield loss show its inadequacy.This thesis based on actual engineering & production case, developing improvement proposal depend on discovering the root cause of the failure and defect mechanism by process data analysis and failure analysis. Promote the product from the engineering stage to mass production while achieving high quality and reducing costs, at the same time, get more experience and promote awareness and understanding of this advanced technology.Thesis focused on two themes:pHEMT SP9T switch low yield due to leakage problems and HBT device poor via contact issue.The first study of SP9T switch, detected RX fail during final test, according to various possible causes of failure the investigation conducted step by step. Regarding assembly, conducted DOE on wire bonding process (4 group factors) for evaluation and based on the results ruled out of assembly may lead to defects. Turned the focus to the wafer analysis, through the use of EMMI、DC test、OBIRCH and FIB, found the path to locate the leakage failure spot. After in-depth analysis found out the root cause is that GaAs technology without CMP process made evaporation process encountered capability limitation led to product failure. From the perspective of optimal design, overlap of the three metal lines in parallel wiring was one of the incentives of the failure. Finally, through amending the design rules and tape out new layout to improve product yield and successfully complete production. The second study of via contact issue, because of the metal used in GaAs technology is pure gold which is difficult to be etched so the metal pattern can only be done by lift-off process, due to lift-off itself process principles, the metal layer presents on the trapezoidal shape. On the other hand, the design of via size and the spacing between the large opening PAD nearby, these factors would challenge etching process and induce via contact issue. Based on this issue study, foundry has established new design rule of the constraints between via size and spacing, and through double photograph to improve the yield of existing product.The above researches of defective products not only enhanced the yield, but also from the both sides of design and process to achieve the product quality.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > General issues > Manufacturing process
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