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10bit DAC Design and Research

Author: WuRanQing
Tutor: ZengXiaoYang；DuanXinDong
School: Fudan University
Course: IC Engineering
Keywords: Digital-to-Analog Converter(DAC) current-steering segmented DNL Latch
CLC: TN792
Type: Master's thesis
Year: 2011
Downloads: 189
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Abstract


Along with the fast development of microelectronic technology and digital processing technology, a big amount of advanced electronic systems are emerging in endlessly. Among of these techniques, Current-Steering plays a more and more important role. It functions as providing the necessary conversion between signals encoding information in bits (digital signals) and signals encoding information in amplitude (analog signals). The development of microelectronic technology requires that DAC must have personalization features as high speed, high resolution, low power and small die size, etc. Therefore, DAC is becoming a bottleneck in this industry now, and an important outstanding issue as well.To meet the requirement of the converting speed and high resolution, this thesis basing on GSMC 0.18μm CMOS Logic Process, designs a 10-bit,200MS/s current-steering DAC. Firstly, this thesis focus on the performance index such as INL、DNL, glitch, SFDR of current-steering DAC. Then, analysis three main architectures:brinary weighted, thermomemter decoded and segmented. Meanwhile, the the current-steering DAC’s random errors, system errors and dynamic performance are analyzed.Here, the current arrays organized as a 6-2-2 segmented architecture, the sector of six most signifcant bits (MSB) and two middle significant bits is thermometer decoded, the other sector of two least significant bits (LSB) is binary weighted. This segmented architecture will get better DNL performance, another advantage is simplified the design of digital decoder circuit, reduceDAC’s area. The current source is designed to meet the requirement of INL, SFDR, INL_Yield, output impendance. To decrease tne matching requirements for the current source, separated current biases are generated and bias the each row. The synchronized switching contorl signals by added the specific latch circuit. The latch also can decrease glitch power and get the better dynamic performance. The cueeent and switches matix use symmetrical sequence to optimized. This thesis run amount of simulation, complete the layout of DAC, the DAC’s area is 290μm*680μm.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Digital circuits > Digital-analog , digital to analog conversion circuit
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