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Optimization of the Deblocking Filter Algorithm in H.264 and ASIC Design

Author: ChenKai
Tutor: MaoZhiGang
School: Shanghai Jiaotong University
Course: Software Engineering
Keywords: H.264/AVC Deblocking Filter ASIC Dedicate Register
CLC: TN492
Type: Master's thesis
Year: 2010
Downloads: 99
Quote: 2
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Abstract


Compared with the MPEG-4、AVS video, H.264/AVC standard is a smaller, based on 4×4 block of discrete cosine transform for image signal compression coding. The independent processing of blocks damaged the image sub-block edge of the inherent continuity. When the compression ratio is high, there is uncontinuous on the image sub-block edges, such discontinuities effects on the performance of the block in the visual. H.264/AVC standard, the introduction of Deblocking Filter used to eliminate blocking effect, while reducing the block effect in the encoding and decoding part of the transmission. Study found that the computational complexity of deblocking filter higher, it is necessary to enable hardware-accelerated decoder to meet the requirements of high-definition standard image.In this paper, based on the H.264/AVC standard, a brief introduction related to the algorithm to analyze the causes of a block effect and block effect on the encoding and decoding process to other algorithms (such as motion estimation, motion compensation, etc.) . Deblocking filter algorithm is a highly adaptive filtering algorithm. From three different adaptive levels of proceeding into the details of the deblocking filter algorithm implementation details. Algorithm is proposed based on analysis of two units at the same time using two identical filter to improve the order of calculation. Design with less on-chip SRAM, an increase of temporary storage at the same time to complete the transpose register unit. Greatly reduce the needs of the entire macroblock filtering cycles. Two design have much the same hardware architecture, but because of filtering in a different order, which the hardware structure used in an improved temporary home storage units and storage units to streamline the conversion.In this paper, the first structure of the RTL hardware implementation and use of integrated 0.25um TSMC technology library. The results showed that the order and structure of the algorithm is able to meet the standards of real-time H.264/AVC high-definition image processing. Complete processing of a macroblock filtering cycles to 128. Has a good application prospects.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > ASIC
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