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Design and Implementation of the FPU in X Microprocessor

Author: GaoZhengKun
Tutor: ZengXianJun
School: National University of Defense Science and Technology
Course: Software Engineering
Keywords: Floating point unit (FPU) Low power consumption Abnormality judgment Mixed adder Booth encoding Carry save addition devices ( CSA ) Wallace tree compressor SRT division
CLC: TP332
Type: Master's thesis
Year: 2007
Downloads: 94
Quote: 1
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In this paper, the design requirements of high - performance , low - power processor X in -depth study of floating-point component architecture and its design method based on the design and support single / double-precision floating-point number floating-point unit (FPU ) the components using a floating-point multiply-add the structure of the passage and parallel execution of the floating point division passage , the floating-point multiply-add passage 3 fully pipelined execution , constituted mainly combined by the adder and multiplier , floating point division pathway using 16 single water performed using 16 SRT division algorithm implementation . Both achieve a the X processor 's floating-point plus less floating point , floating point multiply , floating-point addition to float the whole , storage, loading, etc. 28 floating-point instructions . Floating-point multiply-add paths in the design process , using a double path adder design thinking , judgment and handling of special value , index processing mantissa treatment in the first -stage pipeline station , parallel execution , and follow-up water from the special value processing modules , station control signal; in the specific design process , using the leading 0 calculation and shift parallel complement plus 1 implicitly handling , improved CSA compressor , Wallace tree structure , the 53 hybrid adder , the rounding the logic of the parallel processing method , the optimized design of traditional single- path adder . Demand for high-performance data path design division , in-depth analysis based on 4 SRT division algorithm and its implementation structure by two the SRT algorithm based on 4 serial superimposed based the 16 SRT division structure improvements . Select all the possible quotient value in the first loop iteration via a parallel , obtaining the quotient value of the four redundant form , reducing the critical path delay of the iterative logic . In this paper, the design of FPU by the IEEE-754 standard test vectors , the special operands of each instruction boundary data and random data combination test vectors test , at the module level , instruction-level and system-level simulation verification to ensure the verification adequacy and correctness of the design . FPU design described in RTL code results in 0.13um process its maximum water delay 1.96ns, meet the X processor for high-performance design requirements .

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Electronic digital computer (not a continuous role in computer ) > Arithmetic unit and the controller (CPU)
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