Dissertation > Excellent graduate degree dissertation topics show

Design and Implementation of the FPU in X Microprocessor

Author: GaoZhengKun
Tutor: ZengXianJun
School: National University of Defense Science and Technology
Course: Software Engineering
Keywords: Floating point unit (FPU) Low power consumption Abnormality judgment Mixed adder Booth encoding Carry save addition devices ( CSA ) Wallace tree compressor SRT division
CLC: TP332
Type: Master's thesis
Year: 2007
Downloads: 94
Quote: 1
Read: Download Dissertation

Abstract


In this paper, the design requirements of high - performance , low - power processor X in -depth study of floating-point component architecture and its design method based on the design and support single / double-precision floating-point number floating-point unit (FPU ) the components using a floating-point multiply-add the structure of the passage and parallel execution of the floating point division passage , the floating-point multiply-add passage 3 fully pipelined execution , constituted mainly combined by the adder and multiplier , floating point division pathway using 16 single water performed using 16 SRT division algorithm implementation . Both achieve a the X processor 's floating-point plus less floating point , floating point multiply , floating-point addition to float the whole , storage, loading, etc. 28 floating-point instructions . Floating-point multiply-add paths in the design process , using a double path adder design thinking , judgment and handling of special value , index processing mantissa treatment in the first -stage pipeline station , parallel execution , and follow-up water from the special value processing modules , station control signal; in the specific design process , using the leading 0 calculation and shift parallel complement plus 1 implicitly handling , improved CSA compressor , Wallace tree structure , the 53 hybrid adder , the rounding the logic of the parallel processing method , the optimized design of traditional single- path adder . Demand for high-performance data path design division , in-depth analysis based on 4 SRT division algorithm and its implementation structure by two the SRT algorithm based on 4 serial superimposed based the 16 SRT division structure improvements . Select all the possible quotient value in the first loop iteration via a parallel , obtaining the quotient value of the four redundant form , reducing the critical path delay of the iterative logic . In this paper, the design of FPU by the IEEE-754 standard test vectors , the special operands of each instruction boundary data and random data combination test vectors test , at the module level , instruction-level and system-level simulation verification to ensure the verification adequacy and correctness of the design . FPU design described in RTL code results in 0.13um process its maximum water delay 1.96ns, meet the X processor for high-performance design requirements .

Related Dissertations

  1. Software Approach to Implement Power Optimization in Embedded Handheld Mobile Gis Device,TP311.52
  2. Research on Low Power Techniques of the Instruction Fetching Unit in Embedded Processors,TP332
  3. A High-Performance Audio ∑△ ADC in 65nm CMOS Process,TN792
  4. The Research and Design on Wireless HART Adapter,TN915.05
  5. Low-power、multi-host Interface、multi-layer Design of the LCD Controller,TN873.93
  6. The Low Power Research of Adaptive Receiver of OFDM Digital Base-band,TN851
  7. Study on Mobility Management for IPv6-based Wireless Sensor Networks,TP212.9
  8. Way-predict Based Low Power Cache Design,TP333
  9. Based on low-power embedded Linux system design and implementation of the program,TP368.1
  10. A Low Power Power Management System for Passive RFID Tag Chip,TN402
  11. Heterogeneous data -oriented low-power sensor networks TDMA protocol design and implementation,TP212.9
  12. Near threshold low-power SRAM study design,TP333
  13. Locking rail temperature monitoring node sensing unit design and implementation,TP274
  14. RTL-level and high-performance microprocessor architecture level low power design key technology research,TP332
  15. Soc - based low - power wireless temperature and humidity acquisition system,TN47
  16. Research and Design of the Intelligent Dangerous Gas Detector System,TH83
  17. AES-based security of UHF RFID tag chip research and development,TN402
  18. For low-power radio-frequency identification tag of a memory circuit,TP333
  19. Applied to the gain cell embedded dynamic random access memory adaptive dynamic refresh and write voltage adjustment programs,TP333
  20. Based on 65 -nanometer low-power design and implementation of ARM926EJS,TN402
  21. Audio low-voltage continuous-time Sigma-Delta ADC Research and Implementation,TN761

CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Electronic digital computer (not a continuous role in computer ) > Arithmetic unit and the controller (CPU)
© 2012 www.DissertationTopic.Net  Mobile