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Research of 8051-compatible Core Based Processor IP with AHB Bus Interface

Author: HuXinXing
Tutor: ShenHaiBin
School: Zhejiang University
Course: Circuits and Systems
Keywords: 8051-compatible core Embedded FLASH memory Instruction cache AHB bus interface System on Chip Intellectual Property modules
CLC: TP332
Type: Master's thesis
Year: 2008
Downloads: 103
Quote: 0
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Abstract


10 to 100 MIPS performance needs of the SoC system , this topic 8 8051 compatible kernel based on the expansion of research . For the benefit of the 32 commercial SoC bus IP resources with compatible design reuse , and with the appropriate hardware and software development tools , the topics selected AMBA 2.0 bus specification . The design for the 8051 compatible kernel extensions AHB master interface , so it can be used for AMBA SoC form of a standard 32-bit AHB master device IP . The completion of the internal bridge circuit between 8051 internal bus AHB bus protocol conversion . The package from the processor IP can seamlessly replace the original 32-bit processor , to help speed up the system research and development as well as to build a low-cost SoC solution . While taking advantage of the latest development of the storage process technology , this project uses the 0.18um technology on-chip embedded FLASH memory as program memory , so that the package better performance of programmable processor IP . The subject analysis of the performance bottleneck , add instruction cache design . Parametric modeling instruction cache , 8051 under the framework of the performance characteristics of the instruction cache with changes in the parameters of the relationship of the subject . On the basis of the test results and design constraints , the subject to achieve the direct mapping of a 128 byte capacity instruction cache, so that the system can work on a 176MHz clock frequency . Integrated directly compared to the the embedded FLASH program maximum operating at 47.4MHz with the highest 11.85 MIPS peak performance , and optimize the design to make nearly 3.7 times faster . Achieve the effect of significantly enhance the performance of the system in a limited area of ??consideration . Processor IP design of this project is to complete the design of the 8051-compatible core minimal changes . Through further optimization is expected to enhance the value of the IP . In addition , future research can also expand based on IP .

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Electronic digital computer (not a continuous role in computer ) > Arithmetic unit and the controller (CPU)
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