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Estimating and Monitoring Simulation Research on Power Consumption of Micro-electronic System

Author: LiuJing
Tutor: LiWenShi
School: Suzhou University
Course: Microelectronics and Solid State Electronics
Keywords: Power consumption Power monitoring RTL Gate level UART Switching activity rate Transient current
CLC: TN407
Type: Master's thesis
Year: 2011
Downloads: 24
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Abstract


Low power technology in designing integrated circuits has three important parts, including estimation, monitoring of power and lower power optimizing. Estimation of power, which is one of two main topics in this thesis, plays a role of basic prerequisite to low power optimizing of ICs.There are two aspects to consider estimation and monitoring of power in micro-eletronic system design especially for ICs. On the one hand, the result of power consumption estimation is acquired to guide optimizing while designing a micro-eletronic system. On the other hand, power consumption information is monitored to ensure the reliability of system in micro-eletronic system operating process.There are two main objectives in this thesis. The first objective is that a simulation method for dynamic power estimation of CMOS IC is achieved with practical EDA tools according to the principle of power estimation. The second is that a data acquisition system for high speed and weak current is discussed for applying to monitor power of the micro-eletronic system and for ferthure aiming at demands such as the reliability of micro-eletronic system.Four main contents are researched and discussed in this thesis.（1） The mechanism of CMOS IC power consumption composition and production is analyzed, and then the principle of common dynamic and static methods for power estimation is discussed.（2） On the basis of analysis on existing EDA tools for power estimation simulation, and according to the methods which combine analysis on net list synthesized from RTL circuits with power estimation of macrocell modeling at gate level, the simulation flow of CMOS IC’s dynamic power consumption estimation, which takes the theory of gate switching activity rate （RT） as key point and the UART as an analyzing example, is focused on and elaborated with Quartus II tool for synthesis and ModelSim tool for simulation. （3） The system of power monitoring is built and then the principle and the structure of all modules are concretely analyzed. The current reading and amplifying circuit and the technology of analog/digital sampling at high speed, as the emphasis of these modules, are discussed in detail and simulated with EDA tools.（4） All contents of study on power estimation and monitoring of micro-eletronic system in this thesis are summarized, and the suggestions and ideas for next step of optimizing are pointed out.Typical results with simulation contain following: （1） the average values of powercounters, which clearly record circuit gates’state switching activity and effectively indicate the results of power estimation, are 7986 and 6108 after 4 series of data are respectively transmitted and received; （2） the three op-amp difference amplifying circuit discussed and simulated in this thesis achieves linear amplification as follow formula: Vout=21719.32×ΔVin+2.6759V, when the range ofΔVin and Vout are respectively 1μV100μV and 2V5V; （3） simulation of A/D equivalent sampling technology, which attains a higher sampling speed at 1MHz, is achieved with the technology of parallel time-interleaved sampling with four ADCs which are used for sampling at speed of 0.25MHz.To throw our research conclusions, they are suggested that the study on technology applied on estimation and monitoring of power consumption with practical EDA tools has high reliability in both of the theory and the reality for future ASIC design.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > General issues > Testing and inspection
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