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The Design and Realization of Error-code Detecting Instrument’s Hardware

Author: XiaFeng
Tutor: KuoYongHong；ZhangQingLi
School: Xi'an University of Electronic Science and Technology
Course: Electronics and Communications
Keywords: error-code single-chip communication system HDPLD
CLC: TN915.06
Type: Master's thesis
Year: 2009
Downloads: 27
Quote: 0
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Abstract


During recent information-booming days, technology of digital of communication has been developed very quickly. The reliability of data transfer becomes more and more important than ever before. Detection and analysis on the error-code is needed to measure the system transfer quality. An error-code detection equipment measures the transfer quality of the system by detecting its error-code damnification level. It is a basic work of telecommunication department to detect the error-code ratio of 2048kbps primary block circuit. The equipment also is a necessary tool in relative research, teaching, and engineering area.This thesis begins with theory analysis of error-code detecting and makes a clear description of how to design and implement both the hardware and software of the system. The signal section mainly complete the test code for generating, sending, synchronization and error detection functions in the implement of the hardware. For the purpose of using this instrument much widely, many testing interface and different transfer velocities are used by this system. The section of the microcomputer’s controlling use 8031 microchip which is Main Processor. It not only read the error signal、counting and calculation,but also control a button and LCD Display Module. In addition, the 8031 chip can control HDPLD for downloading of the real-time configuration. Hardware of rational design can provides this system a general hardware-developing platform.This thesis is based on design think of HDPLD. According to the design principle of software radio, the testing code sending and receiving in this system is implemented by HDPLD based on SRAM structure. This makes the developing of hardware "softening". By using HDPLD technology in this system, not only the circuit is much simple, but also improve the design efficiency. It can reduce design costs and investment risks. By a big amount of calculation on the data comes form the measure of the 2048kbps primary block circuit, an error-code ratio calculation formula is concluded. In this step, a new interpolation algorithm that works faster and more accurate is used to get a better performance. For the purpose of using this instrument much widely, many testing interface and different transfer velocities are used by this system. So that it can do the error-code detecting of many different communication equipments for both the industry and education purpose. The error-code detecting instrument controlled by single-chip has some distinct advantages, for instance, it is accurate, low power-consuming, space-saving, and its price performance ratio is high.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Communicate > Communication network > General issues > Testing, operation
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