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The ferroelectric memory (FRAM) , the ferroelectric materials used in integrated circuits , made ??of the novel non - volatile memory . Due to the characteristics of the material , it also has a high-speed, high-density , high reliability , low power consumption and good anti-radiation characteristics advantages , either as a stand-alone memory used in instrumentation , also can be used as embedded memory applications on a smart card , can be widely used in the field of identity cards , aviation , transport , post and telecommunications, finance, office systems , and has broad market prospects , industry and academia recognized as the most promising new generation of non - volatile memory one . FRAM design and implementation of methods to solve the key problem , the papers provide a basis for the design and implementation of high-performance FRAM study ferroelectric memory cell array structure design , and under the existing conditions , the storage unit the water and part of the process test . First , the application of numerical models of the ferroelectric capacitor , use the H-SPICE circuit simulation tools , simulation analysis of the memory cell structure to determine the capacitance of the storage unit , the bit line capacitance and the imaginary unit optimization design size ; and , in the memory cell structure simulation based on a new type of the chain storage unit structure , on the basis of maintaining the advantages of the traditional chain structure of high -density , low power consumption , high reliability , and low- voltage operation ; then, based on the actual process conditions develop a process flow of lithography mask level and layout design rules , and on this basis , to complete the layout of the circuit structure of the storage unit , and water results of testing and analysis , summarize , and discuss the existing problems ; Finally, the size of 4 kb of the design method of the ferroelectric memory module to determine the circuit structure of the basic circuit configuration of a peripheral circuit , the storage unit , the read and write timing , the storage array structure and its circuit parameters design process , etc. , and its the simulation optimization .
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