Design For Testability - Dissertation

About 111 item dissertation in line with Design For Testability query results,the following is 1 to 50(Search took 0.01 seconds)

The Implementation of DFT for a High-performance Processor,WangDan/National University of Defense Science and Technology,0/24
Research of Scan Chain Inserting and Test Wrapper Installing in IP Core Design for Testability,JiangYueMing/Harbin University of Science and Technology,0/6
Low-cost and-power Test for Digital Circuits,WangWeiZheng/Hunan University,0/94
Application of Folding Counters in SoC Test,LiZuo/Hefei University of Technology,0/6
A Low-Cost Delay Testing Methodology Based on Scan Chain Disabling Technique,WangZeCheng/Hunan University,0/6
Research on Low Cost Test Method for RTL Data Path under Power Constraints,TianBin/Hunan University,0/3
The Research on Test Pattern Generator Based on Self-feedback,GuoMiaoMiao/Hunan University,0/22
Integrated Circuit Low-power Design-for-testability Analysis and Implementation,HuangLuHui/University of Electronic Science and Technology,0/18
Research on Multi-Fault Test Generation Algorithms and Design for Testability of Digital Integrated Circuits,WuLiHua/Harbin University of Science and Technology,2/567
Architecture of Design-For-Testability and Its Optimization for System-On-Chip,WangYongSheng/Harbin Institute of Technology,6/766
Low Power MP3 Decoder and Its Design-for-Testability Techniques,ZhouJinFeng/Institute of Computing Technology,5/484
Research on the Design Optimization Techniques for System-On-Chip Testing,ZhangHong/Xi'an University of Electronic Science and Technology,7/744
Research on Design for Testability Based on the Framework of SOC,XuLei/Tsinghua University,5/772
Research on the Realization of the Channel Receiving Chip in Cable DTV,XuYuanXin/Zhejiang University,1/437
Research and Design of High Performance Digital Signal Processor,LiTao/Northwestern Polytechnical University,3/765
Path Delay Fault Testing for Arithmetic Circuits,YangDeCai/University of Electronic Science and Technology,1/189
Research on Accumulator-Based Built-In Self-Test for DSP Data Path,XiaoJiXue/University of Electronic Science and Technology,0/261
Research on Algorithms of Test Pattern Generation for Digital Integrated Circuits,HouYanLi/Harbin Engineering University,2/277
The Research on Reconfigurable SoC DFT Structure and TLB Test Scheduling Strategy,ZhangJinYi/Shanghai University,0/221
Optimization Technology of Design for Diagnostic Strategy Based on Dependency Model,YangPeng/National University of Defense Science and Technology,19/459
Research on Test Points Selection for Analog Fault Dictionary Techniques,YangChengLin/University of Electronic Science and Technology,0/133
Study and Design of Binary and Ternary Circuits Based on the Resonant Tunneling Device RTD,LinMi/Zhejiang University,0/113
Research on Design for Testability and Test Techniques of Network-on-Chip System,ZhaoJianWu/University of Electronic Science and Technology,1/202
Research of a BIST Scheme Using Test Patterns Applied by Circuit-under-Test Itself,OuYangXiong/Hunan University,2/101
Research on ATPG Based on Test Vectors Applied by Circuit-under-Test Itself,LiuQin/Hunan University,2/122
The Researches on Mixed-Signal Test and Design for Testability,PangWeiQu/Hunan University,2/266
Research on the Design for Testability of the Digital Core of the Interphone Transceiver and the Verification of Its Interface Circuit,ZhangZuoJie/East China Normal University,0/166
Deterministic BIST and Delay Fault Testing for Digital System,ZhaoYang/Tsinghua University,0/90
Study of Embedded Memory DFT Based on BIST,XuJinRong/Beijing Jiaotong University,7/274
Digital circuit test generation platform for research and application of design for testability,DengYuDan/Nanjing University of Aeronautics and Astronautics,1/397
Research on Technology of Design for Testability and Application,XieMingEn/Nanjing University of Aeronautics and Astronautics,3/740
Research on Test Generation Algorithm for Delay Fault and I_DDT Test Experiment,CaiShuo/Hunan University,0/58
The Design and Verification of Embedded DSP Processors,LiBaoFeng/Hunan University,6/305
Core-test Methodology and Application in SOC Design,MengQing/Zhejiang University,12/459
Digital Circuits Design Based on RT Quantum Devices,LinMi/Zhejiang University,2/85
The Application and Research of Software Testing in the Telecommunication Monitoring System,FengLi/North China Electric Power University (Hebei),2/143
Computer hardware circuit design for testability and automatic test to achieve,CaiJian/Northwestern Polytechnical University,3/401
Research and Implementation of embedded microprocessor design for testability,GaoShuJing/Qingdao University,3/208
The Design for Testability and the Circuit of DSPC50,ZhuXiaoLi/Hunan University,4/107
The Research on Design for Testability of FPGAs,WuJiJuan/Harbin Engineering University,0/317
A Fast and Low Power Consuming DFT Design Method Based on Scan Array,ZhangLei/Harbin Engineering University,0/95
Study of Embedded Memory DFT Algorithm Based on BIST,YaoJun/Harbin Engineering University,7/282
Research on High Level Test Synthesis Based on PSA,WangGuanJun/Harbin Engineering University,0/42
The Study on Built-in Self-test (BIST) for Integrated Circuits Based-on Multiple Scan Chains,LiuJun/Hefei University of Technology,1/246
A Research about System-On-Chip’s(SOC) Design for Test,ChenYeRong/Jilin University,0/235
Research on DFT Technique for Embedded SRAM,XuZuo/Zhejiang University,2/267
Testability Analysis on Complex Digital Circuit Board Based on Boundary Scan Technology,ChengYunBo/Xi'an University of Electronic Science and Technology,6/413
Executing Module Design and DFT of 32-bit RISC CPU,ZhaoQiong/Hunan University,2/417
Research of Design for Digital System Testability Based on Boundary-Scan,YuDeWei/Harbin Institute of Technology,3/444
The DFT and Test Generation of Garfield,JinZhiGang/Southeast University,1/128