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With the invention of the transistor at Bell Labs in 1947, the extraordinarily rapid development of microelectronic technology, has entered the era of VLSI. In China, as the information industry based microelectronic technology, the speed of production and research has been greatly accelerated, to penetrate deep into all aspects of economic life. From mobile phones, image processing, speech processing, synthesis of computers to digital cameras and other digital products, all left traces of microelectronics technology. Static memory (SRAM), a as digitization family in, in recent years has been considerable development. It is as essential in the semiconductor memory products, in the computer, telecommunications and other high-speed speed data exchange system has been widely used. According to statistics, the current memory market to account for 35% of the entire semiconductor market, and static memory accounted for about 15% of the total memory, and with improvements in technology and technology advances, the annual increase rate of 10%. Static random access memory as an the IC field extremely important part of its long-term unremitting research and development has far-reaching significance. Dual-port static memory, it uses two independent sets of address, data and control bus, while allowing two independent entities (such as two processors) its access to the dual port memory, compared with a single-port memory, the access to double the efficiency. Static memory access speed from the address input to the data output of the critical path decision. Including the address buffer, a decoder, a storage unit, the sense amplifier and the output buffer circuit. The storage unit is the core part of the memory, the structure is relatively fixed, its performance is often determined by the existing level of technology. SRAM design process, it is more of a focus on the decoder, sense amplifier and peripheral circuits optimization to improve the performance of the memory. Design a 1M (128K x 8Bit) dual-port memory, the paper introduces the structure and working principle of the dual-port memory, focus describes the dual-port memory arbitration control circuit, discussed in detail in the storage unit, the sense amplifier, decoder the design. Analysis of the impact of memory speed and power consumption reasons, and the corresponding optimization measures, and strive to be improved through the improvement of the structure of the peripheral circuit of the entire memory performance. 0.5um CMOS standard process conditions by Hspice and Hsim, simulation, simulation results show that: in the typical operating conditions (VDD = 5V, T = 25 ° C), the data access time of less than 15ns typical memory dynamic power consumption of 150mA, the static power consumption of 50mA, the design parameters are to reach the desired objectives. Therefore, in the same process conditions, the memory has the characteristics of high-speed, low-power, memory research and development in the future has a certain reference. The paper is divided into five chapters, the first chapter introduces the development of memory and the memory system architecture; second chapter describes the design and optimization of the decoder; Chapter sense amplifier design; Chapter storage unit arbitration control circuit design process; fifth chapter discusses the dual-port memory, the last part of Outlook and summary.
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