Dissertation > Excellent graduate degree dissertation topics show

Research and Design of High-Speed, Low-Power SRAM

Author: ShiLiang
Tutor: YuZongGuang
School: Jiangnan University
Course: Microelectronics and Solid State Electronics
Keywords: Static memory Storage unit Sense amplifier Decoder
CLC: TP333
Type: Master's thesis
Year: 2007
Downloads: 194
Quote: 1
Read: Download Dissertation

Abstract


As microelectronic technology continues to evolve, the memory showing a high level of integration, fast, low-power consumption trends. Static random access memory (SRAM) as a memory extended family has been considerable development in recent years. It is indispensable as the semiconductor memory, a class of products, widely used in the computer, communications, and other high-speed data exchange system. The data show that the memory market accounted for 35% of the entire semiconductor market, accounted for about 15% of the total variety of memory and static random access memory, and with the improvements in technology and advances in technology to increase the speed of 10% annually. Therefore, in-depth study of the static random access memory has far-reaching significance. The access speed of the static random access memory by the address input to the data output of the critical path decision; critical path includes an address buffer, decoder, the storage unit, the sense amplifier and the output buffer circuit and the like. The storage unit is a core part of the memory, the structure is relatively fixed, and its performance is often determined by the current level of technology. So, in the SRAM design process, pay more attention to improve the performance of the memory key on the periphery of the decoder, sense amplifier circuit optimization design. The SRAM design generally weigh between speed, area, power consumption of the three, and strive to achieve an optimal value. Designed a 256Kb static random access memory. First, the structure and working principle of the static random access memory, focus on the storage unit, decoder, sense amplifier, hierarchical bit line architecture design. By analyzing the impact of memory speed and power, the corresponding optimization measures, through the improvement of the peripheral circuit structure and improve the performance of the entire memory. Finally, in a 0.25μm CMOS standard process conditions, the system by Hspice and Hsim, conducted simulation. The simulation results show that: in the typical working conditions (the V DD = 2.5V, T = 25 ° C), the data access time of less than 12ns. Various design parameters to achieve the expected goals. Therefore, under the same process conditions, the memory has the characteristics of high-speed, low-power memory of future research and development has a certain reference. Text is divided into six chapters, the first chapter introduces the classification and development overview of the memory; given in Chapter II of this paper the design of static random access memory system architecture; Chapter SRAM critical circuit design; Chapter stored array optimized design; Chapter for the the memory overall design and simulation; final chapter Conclusion and Outlook.

Related Dissertations

  1. The Optimization of AVS Video Decoder on the PC Platform and Improvement of Field Decoding,TN919.81
  2. Embedded video decoder motion compensation process data layout optimization,TN919.81
  3. The Research and Implementation of a 65nm High-Performance SRAM,TP333
  4. 8ns 4M_bit High Reliability of Static Random Access Memory,TP333
  5. The Implementation and Optimization of MPEG-4 AAC Decoder Based on NIOS II,TN764
  6. Based on DVB-T standard digital-analog integrated television signal receiving system design,TN948.55
  7. Study on Project Management in Whole Process for Pumped-storage Unit Maintenance,F426.91
  8. The Circuit Design and Implementation of the Sense Amplifier in Nano-Crystal Memory,TP333
  9. Research and Design of Embedded Streaming Media Video Player System over H.264,TN919.82
  10. The Implementation and Optimization of AVS Video Decoder on DM642,TN764
  11. Design of Electric Pan/tilt/zoom Controller Based on Microcomputer AVR,TP277
  12. Research on 125KHz Access Control Reader,TP273.5
  13. Based on multiple optical orthogonal code optical label generation and experimental study,TN929.1
  14. Based on Nios Ⅱ MP3 decoding Research and Implementation,TN912.2
  15. Implementation and Parallelization of H.264/AVC Decoder on TILE64 Multicore Platform,TN919.81
  16. The Design and Implementation of High Speed SRAM in L1 Cache tag Under 65nm Process,TP333
  17. Design of Fpga-based Video Capturing System,TP274.2
  18. AAC decoder synthesis filter bank design and implementation,TN764
  19. Research on the Energy Storage Unit and Its Management System of Hybrid Excavator,TU621
  20. DTMB -based error correction code decoder Research and Design,TN911.2
  21. The Design and Verification of Motion Compensation Based on MPEG2,TN919.81

CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Electronic digital computer (not a continuous role in computer ) > Memory
© 2012 www.DissertationTopic.Net  Mobile