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Study of the GIDL Current and Related Reliability Issues for Ultra-deep Submicron CMOS Devices

Author: ChenHaiFeng
Tutor: HaoYue
School: Xi'an University of Electronic Science and Technology
Course: Microelectronics and Solid State Electronics
Keywords: gate-induced drain leakage tunneling current interface state generation current oxide charge
CLC: TN386
Type: PhD thesis
Year: 2008
Downloads: 226
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Abstract


The gated-induce drain leakage (GIDL) current has beacome one of the serious obstacles to the device scalling and power consumption while it acts as a high-efficiency write/erase opration in EEPROM. The reliability issues related with GIDL current degrade as the device becomes smaller in the untra-deep micron CMOS process. This dissertation deeply and systematically studies the phycical machanism of GIDL current and the related reliability issures in MOSFET’s fabricated by 90nm CMOS process.The dissertation begins with discussion of the physical mechanism of electron tunelling the forbidden band and the dependence of GIDL current on the electric field. On the basis of simulation, the effects of the thickness of gate oxide and the dopping dose in the LDD region on the the electric field are studied.The difference between the influences of the drain voltage VD and the gate voltage VG on the GIDL tunneling current is dealt with by the symmetry method. What is called the symmetry method is: we get the GIDL tunneling current’s transfer curve with the fixed VD and the GIDL tunneling current’s output curve with the fixed VG, where VD of transfer curve equals VG of the output curve. It is found that the difference between ID of transfer curve and that of output curve, DIFF, versus the drain-to-gate voltage VDG shows the shape of peak. DIFF implies the different influences of VD and VG on the GIDL tunneling current. It is due to the different hole tunneling in the lateral direction at the overlap region interface under the two conditions. The maximal DIFF, DIFF,MAX, varies linearly with the VDG in semi-natural logarithm coordinates. DIFF curve shifts upwards as the temperature increases. If the oxide charges are holes, DIFF shifts downwards, and vice versa. The shift of DIFF,MAX has the linear relationship with stress time in log-log coordinate.GIDL tunneling current method is applied to detect the damage at the overlap region. Under the low gate voltage (LGV) stress, the threshold voltage VTH increases in the ultrashort (90nm) and ultrathin(1.4nm) LDD nMOSFET’s. The results are opposite to the degradation phenomena of conventional nMOSFET in this case of stress. By analyzing the GIDL tunneling current before and after stress, it is confirmed that the LGV stress is still the hole-injection stress in ultrashort and ultrathin LDD nMOSFET’s. In addition, it is also found that the maximum substrate current Isub,max stress is a hole-injection stress in the ultrashort and ultrathin LDD nMOSFET using the GIDL tunneling current method.The behaviours of the GIDL stress in the LDD nMOSFET are studied. In the LDD nMOSFET’s with 1.4nm-thick gate oxide, the GIDL stress generates the oxide trapped holes and interface states around the overlapped region, it results in the increase of VTH. During the alternating process, the recovery of VTH depends mainly on the hole-induced recovery of carrier mobility increase. Moreover, the results of recovery depend on the roles of carrier mobility increase on the VTH degradation. On account of the different locations of hot holes-induced damage and their different influences on recovering the degradation induced by hot electron injection (HEI), LGV hot hole injection (LGVHHI), GIDLHHI, substrate HHI (SHHI) in ultrashort and ultrathinl LDD nMOSFET’s are divided into two sorts: holes created locate at the interface in the LDD region (i.e, LGVHHI and GIDLHHI) and holes created locate at the interface in the channel region, i.e. SHHI.During the study of the GIDL generation current of LDD nMOSFET and LDD pMOSFET, the maximal generation factorγis proposed and the characteristics of GIDL generation current is shown usingγ. It is found that the generation current peak decreases as the stress time increases under the high-gate-voltage(HGV) stress (it injects electrons in the nMOSFET and holes in the pMOSFET) in the 4nm-thickness LDD MOSFET. For the case of nMOSFET, the decrease has the same trends with the increase in the density of oxide trapped electrons. It ascribes to the dominating oxide trapped electrons which reduce the effective drain bias so that lowering the maximal generation rate. Ignoring the interface states reasonably, the density of the effective trapped electrons affecting the effective drain bias is calculated using this new model. This new model also holds for the case of the pMOSFET under the HGV stress.

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