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Research for Hardware Implementation of SHA-3Algorithms

Author: LiangZuo
Tutor: BaiGuoQiang
School: Tsinghua University
Course: Electronic Science and Technology
Keywords: Hash Function SHA-3 hardware implementation BLAKE Keccak Skein
CLC: TN918.1
Type: Master's thesis
Year: 2011
Downloads: 144
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Abstract


With the development of the information technology, the security of informationbecomes a more and more remarkable topic. As the foundation, cryptography andcryptographic technology take a very significant role in information security. Incryptography, hash function is one of the most important tools which are used fordigital signatures, password protection, message authentication and so on.Nowadays, with the development of cryptanalysis, the security of hash functionhas been weakened seriously by mathematic attack. In order to select a new StandardHash Algorithm (SHA-3) which supplies more security, a public competition wasorganized by NIST in2007. Up to now,5candidates have entered the final round. Inour research, we focus on hardware implementation of these candidate algorithms.In this paper, we present the common top-level structure for all the SHA3candidates at first. We designed the data path and state machine, which can supportthe functions of data input, message padding, process control and data output. Wealso accomplished the hardware implementation of BLAKE, Keccak and Skeinalgorithms, simulation has been completed with Model-Sim.For the different applications, we opitmized the designs of the three algorithmsin two dimensions: one is high speed version which for high-performance processor,the other is low area version which for smart card etc. In high speed version, themethod of “parallelism” is used, and data read and data operation are processedconcurrently. In low area version, we take the way of DMA. Thourgh a internal statemachine, the algorithm can work while the similar operation cells was multiplexed asmuch as possible.Base on Xilinx Vertex-5xc5vlx220and SMIC90nm CMOS technology, wegive the result of synthesis on FPGA and ASIC. In high speed version, thethroughput of BLAKE, Keccak, Skein can reach4.012Gbps,17.51Gbps and3.07Gbps respectively. In low area version, we can reduce the area to0.053mm2，0.072mm2and0.086mm2。In addition, we do some primary research on countermeasures against Power Analysis attacks for SHA-3algorithms. Base on data masking method, a circuit ofKeccak which against Power Analysis attacks is designed.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Communicate > Confidentiality of communications and communications security > Theory
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