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Research and Implementation of Dynamically Reconfigurable Cache Coherence Protocol for Many-Core Processor

Author: ZhouChuan
Tutor: FuYuZhuo
School: Shanghai Jiaotong University
Course: IC Engineering
Keywords: many-core processor Cache coherence Token coherenceprotocol dynamically reconfigurable
CLC: TP332
Type: Master's thesis
Year: 2013
Downloads: 96
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Abstract


With the development of IC technology and micro-architecture, themany-core processor has become an important direction for future research,and is the hot topic of the current academic and industry. Due to the largenumber of processor cores, How to take advantage of the huge computingresources, to overcome the memory bottleneck caused by large scale of theprocessor and to address the problems of dynamic resource requirement fordifferent tasks and phased resource requirement for the same task havebecome major problems to be solved in many-core processor.The main work in this paper includes:1) Use dynamic subnetting tosolve the resource utilization problem and dynamic resource requirementinmany-core processor.2) In order to support the dynamic subnetting,designthe dynamically reconfigurable Cache coherence protocol based on Token.3) Implement the dynamically reconfigurable Cache coherence protocol inGem5and verify the whole design.In this paper, basing on subnet, the dynamically reconfigurable Cachecoherence protocol will work better than Token coherence and Directorycoherence. Experiment results show that the execution time of dynamicreconfigurable Cache coherence protocol is10%less than Tokencoherence while it will reduce over30%of the communication cost inNOC compared to Directory coherence. Therefore, this dynamicallyreconfigurable mechanism makes Token Coherence applicable inmany-core architecture.

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Electronic digital computer (not a continuous role in computer ) > Arithmetic unit and the controller (CPU)
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