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CAN bus communication is one of the most widely used technology in industrycontrol area, design based on the CAN bus technology has to obey the standard, inorder to meet the requirement of different system. for that, it’s very important todesign a CAN core controller which obeys the ISO standard, and it does harm tosystem steady and timing accurately. in this paper, a CAN controller based on the2.0protocol has been designed, in order to supply a nation gap for our country.Controller contains all the working mode, including data transmitting, errordisposing, hang on transmitting, remote requirement etc. this paper designs the statemachine and mode transform for folding frame and standard frame, make delicateplan for data transmitting between MCU and controller through CAN bus.CAN hardware resource for data disposing contains many layers such ascontroller, bus, work station, MCU etc. for the data needs to be packed, the MCUcannot afford so much work, so, data form logic, CRC, decoding, TXD and RXDcircuit should be added into the plan, then, design the whole order set and registers,and construct the complex framework for CAN controller based on the verilogbench.The whole design process is taking on the circuit physical design area, it inflectsa intact IC design process, so many design tools such as NC-verilog, Designcompiler, primetime, formality, ESD test equipment has been used to do the design.through the whole process of design and test, an intact netlist has been made to formthe GDS-II. so, the design is a flow sheet.TX and RX circuit with high speed, hardware resource steady has been used inthe chip, instead of the resource which is taken by the CAN transfer, clean up theredundant circuit resource through DC and FM tools and redesign the framework ofthe chip, the proportion and power dissipation has been reduced effectively, improvethe efficiency and function of the chip, and has good comtibility through DIPencapsulation, fit the requirement for so much system, reduce the degression of thetest. So many tools has been used to verify the validation of the design, packedextreme data in the frame, produce and simulate the interrupt and data transfer incomplex situation, restrain the data route with the condition of the database, receivethe signal at data interface, see the work situation of the frame and state transmitting,then demonstrate and analysis the software and hardware resource.
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