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Research and Design of a High-Performance Scalable Public Key Cryptographic Coprocessor

Author: LiMing
Tutor: ZouXueCheng
School: Huazhong University of Science and Technology
Course: Microelectronics and Solid State Electronics
Keywords: Public-key cryptosystem Coprocessor RSA Elliptic curve cryptosystem Montgomery Algorithm Parallel computing Scalability
CLC: TN918.1
Type: Master's thesis
Year: 2011
Downloads: 15
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Abstract


Public key cryptosystem solve the problem of key transmission and management difficulties symmetric cryptosystem, play an important role in the field of information security, digital signature and authentication technologies effectively protect network data transmission integrity and non-repudiation of the parties to the transaction sex. RSA and ECC (Elliptic Curve Cryptography) is one of the two most important and the most widely used public key cryptography algorithm. RSA's security is based on the large integer prime factor decomposition of the intractability of the security of ECC is based on the intractability of the elliptic curve discrete logarithm problem. ECC algorithm is higher than the RSA algorithm, a single-bit security, equal security strength ECC key length smaller than RSA lot of needed storage space and transmission bandwidth, low computational complexity, the power consumption consume less. Because of the unique advantages of the ECC, ECC can be widely used in the broad field of low-end embedded systems to high-end servers, etc.. The performance of public key cryptography algorithm software can not meet the real-time requirements of the practical application, and the key is a very easy to leak. Mainly special the hardware coprocessor way to implement public key cryptography algorithm. The in-depth study of the RSA and ECC algorithms, RSA and ECC algorithm has the same core of basic arithmetic modular multiplication mode subtraction, modular exponentiation operation. ECC point operation can be achieved by the basic operations of these core. On this basis, we propose a high-performance scalable public key cryptography coprocessor is used to achieve the basic operations of RSA and ECC modular multiplication, modular exponentiation point subtraction point calculated doubly and point scalar multiplication operation acceleration, and the entire cryptographic protocols using software and hardware co. The coprocessor core the modulo arithmetic cell array parallel computation, the arithmetic unit of each mold by a high performance can be extended Montgomery multiplication unit and a high-performance scalable mode subtraction unit. Montgomery modular multiplication unit based on this paper, a two-domain unified word processing bit wide high radix Montgomery modular multiplication algorithm, its core multi-processing unit flowing computing architecture to support the dual domain any bit wide operand modular multiplication . Modulus subtraction unit uses the circuit configuration of the word processing bit width, to avoid the mold of a traditional analog subtraction circuit to the reduction step, but optimized for the ECC arithmetic simplifies the addition and subtraction in the ECC arithmetic support dual domain arbitrary bit wide operand mode subtraction. Parallel computing power of the coprocessor mode exponentiation can support parallel binary algorithm and the Chinese Remainder Theorem, ECC point plus point doubly point subtraction in the multiple-mode arithmetic unit based on the parallel scheduling, effective the acceleration of the basic operations of RSA and ECC. The high-performance scalable public key cryptography coprocessor design need to optimize the data path width modular multiplication processing unit cell number and modular arithmetic unit number of the design parameters. The optimization of these parameters need to be carried out in this the coprocessor area and performance trade-offs. 0.18μm CMOS process, co-processors for different parameter combinations, design evaluation, and the method for selecting the optimal parameter set. A more optimized design parameters, this paper specifically designed and implemented the coprocessor chip maximum operating frequency of 250MHz, area 380kgates. Chip test results show that the coprocessor has good computing acceleration performance, using the Chinese remainder theorem to complete a 1024bit modulus exponentiation domain only 232μs, complete GF (p) domain 192bit scalar multiplication only 242μs to complete GF (2m) the 192bit scalar multiplication only 222μs.

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