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Research and Implementation of VMM-Based Verification Platform

Author: YeMao
Tutor: TanYunMeng
School: Huazhong University of Science and Technology
Course: Spatial Information Science and Technology
Keywords: Integrated Circuit(IC) Functional Verification SystemVerilog Verification Methodology Manual Assertion Functional Coverage
CLC: TN407
Type: Master's thesis
Year: 2008
Downloads: 398
Quote: 16
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Abstract


With the booming of the scale and complexity of IC design, the verification of IC is becoming more and more difficult. Although engineers keep updating the technology of the traditional verification methods to adapt to the increment of the size and complexity of IC design, verification is still facing the greatest challenge. Hardware Description Language is used to designs of Register Transfer Level, but Hardware Verification Language needs more abstract characteristic, which causes mutually exclusive direction of development of them and makes the process of design and verification complex. The challenges to verification, to a great extent, promote the development of verification methodology and technology. To close the gap between design and verification of IC, engineers constantly put forward some new technologies, which significantly improve the efficiency of verification.The thesis introduces some concepts and methods in traditional verification and discusses the advantage and disadvantage of them. We also discuss the direction of the development of verification technologies. Traditional verification platform has limitation of long cycle and verbose working. Thus, the thesis researches on the key technologies of verification methodology, of which Constrained-random test makes testbench create stimulus automatically, and finds some bugs you never thought about. Assertions both document and check the design engineer’s assumptions and expectations about the design functionality, and trace the errors in the simulation. Functionality coverage can make a full check of the design and make 100% coverage. Then the thesis puts forward one layered testbench based on transaction. Then the thesis gives a detail analysis of the testbench. Finally, we redesign the verification platform in the realistic project with the SystemVerilog VMM standard library; make a statistic and analysis of the results. The result of this case proves this platform’s feasibility, affectivity, and automation.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > General issues > Testing and inspection
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