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Abstract

The micro/nano size characteristics dimension of IC technology is the mainstream of VLSI production techniques at present and in the future. After entering nanoscale, along with the continuous decreasing characteristic dimension of MOSFETs, some parameters which can be ignored in long channel devices become much more aggressively in short channel devices and have a strong impact on performances of the device. Then people begin to study how to maintain performances of long channel devices when the characteristic dimension of MOSFETs reduced. In order to reduce the short channel effects of short channel MOSFETs, measures like improving devices structure, changing channel doping concentration and reducing gate oxide thickness is proposed. However, it causes the parasitic resistance accounting for larger proportion with the total resistance, as the parasitic resistance of MOSFETs can’t be reduced along with the scaling down of MOSFETs. Therefore the output characteristic and frequency characteristic is reduced.This paper firstly introduces the scaling down trend of MOSFETs characteristic dimension, and the great challenges for the physical limits, process engineering and economic factors. Then improvement of the structure, material and process is considered to achieve scaling down of MOSFETs.On that basis, a model for grooved gate MOSFET with a retrograde channel is proposed and anlyzed. Take grooved gate NMOSFET with a retrograde for example, and compared with the conventional MOSFET, it is verified that it can improve the reliability of deep submicron and ultra-deep submicron MOSFETs and restrain short channel effect, by changing parameters like the concave corner, channel length and channel doping. Moreover, it is more simple than SOI MOSFETs in process. Without any additional process steps and equipment, it can fundamentally solve defects of planar device. But there are also some disadvantages, such as the reducing of drain current driving capability and the increasing of parasitic capacitance. Furthermore, retrograde chanel is introduced. Based on the solution to the Poisson’s equation, super steep retrograde channel and linear variation doping retrograde channel models are set up respectively, then the equations on the surface potential and drain current can be obtained. The model gives the influence of doping profile sharpness on the drain current, saturated drive current, and surface potential. It is infered that adopting retrograde channel takes advantages on restraining short channel effect of short channel devices.The influence of the parasitic resistance on the MOSFETs performance cannot be neglected, because parasitic resistance can’t be reduced by the scaling down of MOSFETs. To more actually analyze performance of grooved gate MOSFET with a retrograde channel, we study it’s source and drain parasitic resistance, and analyze the influence of parasitic resistance by changing parameters, in order to better practice device design and improve device performances. In the process of parasitic resistance anlysis, first the parasitic resistance model of conventional MOSFETs is introduced, then bases on above the design is improved, and the parasitic resistance model of grooved gate MOSFET with a retrograde channel is introduced. In the condition of different concave corner, length and width of souce and drain, this paper calculates changes in the source and drain parasitic resistance of grooved gate MOSFET with a retrograde channel, then compares the advantages and disadvantages of parameters, and finally obtains optimal value, to improve the performance of the devices.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Semiconductor technology > Field-effect devices
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Study of Grooved Gate MOSFET with a Retrograde Channel

Abstract

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