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The Design of 16 Bit∑△ADC

Author: YeYing
Tutor: ZengJianPing
School: Hunan University
Course: Microelectronics and Solid State Electronics
Keywords: Modulator Noise shaping Idle tone Bandgap reference Switched capacitor integrator Decimation filter Comb filter
CLC: TN792
Type: Master's thesis
Year: 2008
Downloads: 305
Quote: 3
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Abstract


Σ △ ADC is based on sampling , noise shaping , and decimation filtering technology developed . Σ △ ADC full use of the advantages of modern VLSI high-speed , high - integration , while avoiding components mismatch on the accuracy limitations of the conversion , and the digitized features so that it can be integrated with other digital chip , thus the process with particularity , greatly reducing the cost of the system . This paper systematically Σ △ ADC design and the completion of the design used in the field of high-fidelity audio signal processing a 16bitΣ △ ADC . Σ △ ADC is divided into two parts of the modulator and the digital filter . This article by the noise transfer function of the modulator to be optimized as well as to compare the various modulator structure , improvements and use of a novel 64-fold oversampling rate , the fifth-order monocyclic bit with distributed feedforward , the form of a local feedback the structure of the modulator , non-ideal factors affecting the performance of the modulator at the same time a more detailed analysis. And then design the overall circuit arrangement of the modulator . Finally, consider the actual factors based on turn design clock generation circuit , pre-filter , bandgap reference source , switched capacitor integrator latched comparator and DAC sub-module circuit simulation . On the basis of the principle of the digital decimation filter 52 order FIR compensation filter through the improvement and optimization of the traditional comb filter structure obtained using a new type of variable order non - recursive structure , design , and comb filter attenuation in the passband for compensation. Then design a clock circuit . Σ △ ADC overall circuit design . 0.5μm CSMC process conditions using Cadence Spectre tool with Matlab simulation of the modulator , the results show that the modulator circuit SNR up to 115dB . Adequate noise margin is left for the post- digital part . Through the preparation of the test file using Cadence Verilog-XL in the tools of the digital filter circuit simulation , circuit timing is correct , the data is correct . Written Matlab using Simulink entire ADC system modeling and verification program simulation results show that The system SNR is 99dB, the effective number of bits for 16.20bit . Reached the expected 16bit accuracy specification requirements .

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Digital circuits > Digital-analog , digital to analog conversion circuit
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