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Research and Implementation of Key Techniques of High Performance Floating-Point Unit Designs

Author: ChenFangYuan
Tutor: LiuZuo
School: National University of Defense Science and Technology
Course: Computer Science and Technology
Keywords: Floating - point processing unit Second stars of the detection method BOOTH algorithm Tree multiplier Floating-point multiplier Floating point divider
CLC: TP332
Type: Master's thesis
Year: 2008
Downloads: 150
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Abstract


The past 60 years, with the rapid progress in microelectronics and integrated circuit technology, the microprocessor amazing development, performance rapidly improved. At the same time, in order to meet the high performance requirements of microprocessors, floating-point processing unit (FPU) on the critical path computation speed must be fast enough. Existing processor's floating-point processing unit basically made a very good performance, but there are some problems. In the floating-point processing unit, the floating point multiplication started toward higher hex, higher bits wide, and a higher degree of parallelism of the multiplication algorithm development and therefore the speed of the multiplier and the area directly affects the performance of the entire floating-point processing unit, the need improve and optimize the design of the multiplier in order to improve the overall performance of the floating-point processing unit. Meanwhile, in the floating-point processing unit, division, and square root frequency lower computation is still the performance bottleneck of the entire unit, the more complex structure of the operation is also relatively large, the area and power consumption of the processing unit. This paper studies address the problem of the floating-point processing unit design key technologies. The part of the plot for the floating-point multiplication rules proposed pseudo 1 transform optimize its control path; Wallace tree multiplier pre-pseudo-plus method, not only to reduce the part of the accumulated delay, but also reduce the circuit complexity; lookup table method and Goldschmidt algorithm In this paper, on the basis of the multiplier to the design and implementation of floating-point division, and by the control circuit to achieve the FPU of the order, out of order flow, to fully tap FPU resource utilization. Designed in this paper on the use of these design techniques to achieve a floating point processing unit, and its performance analysis and testing to verify the validity and correctness of the design technique proposed in this paper. First, this paper, a key component of the floating-point addition in the floating-point processing unit were analyzed. On the structural basis of the dual path (Two-Path) algorithm, the normalization process for a relatively large delay in the floating point adder results, using leading zero detection algorithm of the two stars detection method proposed solutions to this problem, conducted leading zero detection design, shorten the delay, simplify circuit design. Secondly, for the 64-bit multiplication, optimize floating-point multiplication part of the product generation circuit in the control path, partial product generated rules to control the path of the pseudo-1 conversion strategy to reduce delay, simplify circuit design, reduce the area and power consumption. Meanwhile, in the conventional Wallace tree multiplier, the introduction of a partial product compressed into the bit in the array during the prefetch and low discarding strategy proposed pre pseudo add method, not only reduces delay, but also reduces the circuit complexity sex. The combination of pipeline design technology, this improved design program can be completed in a single cycle of single-precision or double-precision floating-point multiplication, meet the fast three-dimensional graphics, high-speed floating-point processing unit higher performance requirements. Based on the water part of the floating-point multiplication, combined with a look-up table method and Goldschmidt algorithm design and implementation of floating-point division. 5 based on the realization of the key components of the above-mentioned floating, each floating-point arithmetic of the water control. The iteration order execution control signal on the FPU floating-point division, the outflow of out-of-order design and implementation. Make full use of the FPU resources, to improve the performance of the FPU. Finally, on the basis of the above-mentioned high-performance floating-point processing unit design key technology, design and implementation of a high-performance floating-point processor, This paper presents a variety of key technologies to achieve. Through testing and simulation, test results show that the proposed design floating-point processor can meet the requirements on the performance, area.

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Electronic digital computer (not a continuous role in computer ) > Arithmetic unit and the controller (CPU)
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