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The testability design technology in the chip design

Author: ZhangYongGuang
Tutor: WangKuang
School: Zhejiang University
Course: Communication and Information System
Keywords: Design for testability Controllability Observability System-on-Chip (SOC) Test Scheduling Testing resources
CLC: TN402
Type: Master's thesis
Year: 2005
Downloads: 801
Quote: 2
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Abstract


Testing of integrated circuits is becoming increasingly difficult as the complexity of the integrated circuit technology and design complexity rises , has become the primary means to solve the problem of chip testing and design for testability . IP (Intellectual Property) core reuse - based on-chip (Soc) chip testing issues become more prominent , but also new design for testability and design process of integrated circuits can be . This article first briefly integrated circuits a variety of commonly used test methods , failure mechanisms and fault models , content and design for testability relative to the standard , then outlines common testability design techniques , such as scan design for testability within built in self-test , boundary scan . The next combination OR1200 chip circuit structure , analyzing the advantages and disadvantages of various methods of design for testability , OR1200 chip design for testability program focuses on . Also , test vector generation method to test the effectiveness of the design for testability , the results showed that the design for testability , design for testability well reach OR1200 chip testing requirements . The the CMOS device enters the UDSM stage , integrated circuits continue to the high level of integration , the development of high speed, low power consumption , making integrated circuits are facing new challenges in the testing and design for testability . This paper analyzes the difficulties faced by the testing and design for testability ; then discuss a system-on-chip (SOC) design testing and design for testability , and testing and design for testability direction of future development prospect . Introduced SOC test with different priorities , resources , core constraint - based optimization model for large-scale SOC test SOC test scheduling with neural networks , exploratory random search technology while taking advantage of the neural network has been improved . The simulation results show that the improved neural network can not only solve the SOC test problems , the optimal solution can be found within a reasonable computation time and has excellent performance to solve the SOC test scheduling problem .

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > General issues > Design
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