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A Congestion Driven High Level Re-Synthesis Method after Floorplanning

Author: WangWenJun
Tutor: BianJiNian
School: Tsinghua University
Course: Computer Science and Technology
Keywords: Routing congestion High - level synthesis And then integrated Floorplanning
CLC: TN402
Type: Master's thesis
Year: 2005
Downloads: 95
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Abstract

The integrated circuit manufacturing process has entered the deep submicron era, interconnect line became one of the decisive factors affecting the performance of the circuit. With the increase in the number of layers of wiring routing resources more abundant. However, more complex circuit designs and higher performance requirements of the local traces still can not avoid crowding. Traditional IC design flow, the high level of the design of the front and back-end physical design is completely separated from the front end of a high-level synthesis stage with no regard to the alignment of local congestion problems. The results of the high-level synthesis, no wiring congestion optimization. This will cause the enormous pressure of the physical synthesis stage, and it may not be able to successfully eliminate all traces crowded. Circuit topology have been identified in high-level synthesis can not be modified in the physical design stage circuit topology has a great influence on the distribution of the traces. Physical design can not be successfully resolved crowded wiring can only enter the huge iterative process, re high-level synthesis, this is an extremely time-consuming process, and can not guarantee the convergence of the iteration. The traditional design process to improve the use of high-level and then integrated approach, the physical design and the combination of high-level synthesis, consider the wiring congestion problem at the level of high-level synthesis. This method prior to the start of the physical synthesis stage, put alignment needs as evenly distributed as possible to the chip physical synthesis stage of the local crowded alignment to minimize the possibility; traces and even local congestion, there are ample space to facilitate physical synthesis tools to solve it. Improved process in addition to the huge traditional process can not guarantee the convergence of the iterative process. The high-level synthesis results reflect the interconnection lines and other physical indicators of demand, provide a good initial solution for the subsequent physical synthesis stage. This paper presents a new oriented Congestion floorplanning high-level and then integrated approach. The algorithm first uses floorplanning tools unit location information; then using a probabilistic model for estimating the demand distribution traces, and to evaluate the uniformity of the distribution; Finally, through high-level integrated method for high-level synthesis results re-scheduling and redistribution, change of the topology of the circuit, thereby changing the trace the distribution of the demand on the chip, to achieve the purpose of the traces demand distributed as uniformly as possible on the chip. The algorithm is based on simulated annealing method. The experimental data show that the present algorithm is able to successfully make the wiring requirements on the chip distribution as uniform as possible.

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