Dissertation > Excellent graduate degree dissertation topics show

Single-phase Adiabatic Circuit

Author: FuJingHong
Tutor: HuJianPing
School: Ningbo University
Course: Communication and Information System
Keywords: Adiabatic circuit Single-phase power clock Power-gating techonology Layout verification
CLC: TN79
Type: Master's thesis
Year: 2009
Downloads: 29
Quote: 0
Read: Download Dissertation

Abstract


With the rapid development of microelectronics technology and portable electronic product, power consumption has become a bottleneck in the development of integrated circuits. Sequential logic circuit, Combinational logic circuit (adder、multiplier and so on) and Memory( including Content Addressable Memory) are the important components of communication circuit, and the core of modern microprocessor, and also the largest component of energy consumption of digital signal processing.Adiabatic circuit is a new low-power circuit design technique, the typical adiabatic circuit contains PAL-2N, 2N-2N2P, ECRL, CPAL, CAL and so on, which all have received a lot of power savings. Single-phase adiabatic logic circuits has been more and more widely used, because it’s clock tree is easy to be produced.There is power consumption for charging or discharging of the node capacitor in adiabatic circuit even if the circuit is in idle mode. In order to reduce energy loss in idle period, a single-phase power control circuit has been presented, which is similar to conventional CMOS technology.As the technology size decreases, the leakage power consumption accounts for an increasing proportion to the total power consumption, and can’t be ignored, so adiabatic leakage power technology are explored. In order to reduce leakage loss of the power control circuit in sleep mode, a single-phase multi-threshold power control circuit has been presented and applied to CPAL sequential logic circuit.Finally, typical circuits are chosed for the layout and verification, which are simulated by TSMC 0.18μm CMOS technology. Cadence’s Virtuoso Layout tools for full-custom manual layout design, Mentor’s Calibre layout parasitic extraction tools and HPICE for Post-layout simulation are used. The Post-layout simulations show that the design of low-power single-phase adiabatic circuits can work well and have good performances.

Related Dissertations

  1. The Design of Low-Power Memory,TN432
  2. The Design of 8 Bits RISC-CPU,TP332
  3. Low-power chip technology and its applications in RFID,TP391.44
  4. Research on Design and Verification for IC Manufacturability in Sub-Wavelength Lithography Circumstance,TN405.7
  5. The Design and Realization of Data Cache in 64 Bits CPU,TP332
  6. Design and Implement of Analog Front-end Circuit for RFID Tag IC,TN402
  7. JPEG Implementation of Still Image Compression Technique,TN492
  8. Research and Design of high performance CMOS bandgap voltage reference source,TN432
  9. Built-In Self Test Research of Digital Circuit,TN79
  10. Video Surveillance System Hardware Design Based on Signal Integrity Analysis,TN79
  11. Research and design of high-performance clock driver circuit,TN79
  12. Extended Compatibilities for Multiple Scan Tree Construction of Digital Circuits Test,TN79
  13. Design and Implementation of Digital Circuit System Based on Multiprocessor,TN79
  14. Physical Design of Digital Part of UHF RFID Tag Based on 0.18μm Process,TN79
  15. The Design of Boolean Logic Gates Based on DNA Computing,TN79
  16. High-Speed Digital Circuit Signal Integrity Analysis and Simulation,TN79
  17. Back-end Design of the Digital Circuit for UHF Passive RFID Tag,TN79
  18. Digital circuit high power microwave (HPM) effects of,TN79
  19. One EPC Gen2 protocol digital circuit hardware implementation, verification and testing,TN79
  20. Research on Circuits Design Method for Error Tolerance,TN79

CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Digital circuits
© 2012 www.DissertationTopic.Net  Mobile