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Wireless local area network (Wireless Local Area Networks, WLAN) is the product of the combination of the computer network and wireless communication technology, through the use of RF (Radio Frequency, RF) technology constitute a local area network, not only be able to provide all of the features of the traditional wired LANs, but also can be used radio channel to the access network, provides a convenient channel for communication mobile, personalization and multimedia applications, and become one of the effective means of broadband access. WLAN technology data, voice and video signals can be transmitted in the air, making the original wired network encountered problems solved. Nowadays, the wireless LAN indoor data transfer can reach several tens of meters to hundreds of meters range, can also be transferred to a distance of tens of kilometers in the outdoor. From the the WLAN value and prospects can also be applied to the physical layer of wireless LAN RF receiver IC has a great prospect. How to achieve low-cost, high-performance radio frequency (RF) receiver terminal is a challenging significance. The RF receiver system of a wireless communication requirements in ensuring the extremely high sensitivity of the premise, as far as possible to improve the linearity of the receiver, so that the output signal of the system to minimize distortion, the BER (Bit Error Rate, BER) minimum. Further, the receiver system also requires wide show possible RF input and output dynamic range, so that the receiver and adaptable, and better anti-jamming capability. In the past, usually using GaAs fabrication RF receiver integrated circuit, mainly because this process has a high operating frequency, low noise advantages. With the continuous advancement of CMOS technology in recent years, the the CMOS frequency characteristics and noise characteristics gradually improved, it has become possible RF front-end receiver circuit using CMOS technology. CMOS process with low cost, small size and high performance. The produced RF CMOS process the circuit easy and digital signal processing baseband Circuit compatible, in line with the trend of the development of system-on-chip (System on Chip, SOC). IEEE802.11a standard RF front-end receiver circuit TSMC0.18μm CMOS-based process design, and layout design. Papers starting from system-level design, first discuss the zero-IF (direct conversion) structure, superheterodyne structure and two frequency structure works as well as a variety of structures for high and low the circuit module performance requirements structure. In the above structure, the existence of a variety of non-ideal characteristics such as noise, the image frequency (direct conversion mirror frequency does not exist), nonlinear, distortion, impedance mismatch, etc., articles have carried out a systematic analysis of. At the same time, lists the important parameters of system architecture, such as noise figure, mirror frequency rejection ratio, gain, gain compression point, 3rd order intercept point, as well as input and output impedance matching. The IEEE802.11a standard conduct a careful analysis of the system parameters to determine the overall framework of the RF receiver. Subsequently, the paper design of each circuit module includes a low noise amplifier (Low Noise Amplifier, LNA), mixer (Mixer), AGC (Automatic Gain Controller, AGC), the transconductance - Capacitance IF filter (Gm -C filter) and sigma-delta ADC. Active CMOS LNA as the first level, noise performance, gain and linearity greatest impact on the entire link. Therefore, the rational design of LNA is critical. The article also optimize the design of LNA spiral inductors, low resistivity Si substrate, Cu/SiO2 interconnect technology and design the inductor layout structures suitable for WLAN. Mixer as a second-level circuit, linearity, gain and noise impact on the overall circuit is also research focus. Using a Gilbert cell as the core mixer, before the increase of the input buffer stage of the local oscillator signal is amplified, so that the work in the switching state of the transistor has a better switching characteristics, optimizing the linearity of the mixer. The IF filter transconductance - capacitor filter, in order to meet the needs of the large bandwidth of the system. Module AGC AGC referred to as a variable gain amplifier (Variable Gain Amplifier, VGA), to achieve the adjustment of the overall gain of the overall link function, the main basis of the adjustment of the feedback of the digital signal is a digital signal processing baseband. The main parameters of the VGA gain changes the dynamic range and gain step. In this paper, a combination of cascaded differential amplification on the way to achieve levels of gain, based on a feedback signal of the digital baseband, thereby to achieve the dynamic range of 54dB and 1.7dB of gain step. Finally an analog-to-digital converter MASH21b-24b cascade structure, sigma-delta ADC. WLAN requirements, ADC 10MHz signal bandwidth. For such a large bandwidth requirements, if using conventional ADC, such as pipeline ADC, can also achieve an analog / digital conversion, but the power consumption, are very large in size. Sigma-delta analog-to-digital converter with its unique mechanism to relax the requirements for analog circuit design, through oversampling, noise integer and a number of quantizer technology to reduce the noise bandwidth, to improve the signal-to-noise ratio, thereby enhancing the ADC accuracy. The introduction of the non-linear multi-bit DAC using the DWA digital correction method. Cadence Virtuoso layout Editor overall layout of the circuit, and Diva / Dracula verification tools to complete the unit and the overall link DRC (Design Rule Check) and LVS (Layout Versus Schematic) verification. Overall circuit input signals to 5.7GHz, noise figure 9.284dB, input impedance matching S11 is-16dB matched impedance 50Ω VGA input control bit is the default value of 10011, the link gain of 45.95dB and the IIP3 of-16.7dBm maximum input signal amplitude-30dBm, to reach the the WLAN performance requirements. The entire receiver (in addition to the frequency synthesizer) current consumption of 38mA, layout area 3mm × 3mm.
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