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The Nanometer CMOS Interconnect Performance Study Considering Process Variations and Scattering Effect

Author: WanDaJing
Tutor: ZhuZhangMing
School: Xi'an University of Electronic Science and Technology
Course: Microelectronics and Solid State Electronics
Keywords: Nanoscale CMOS Interconnect Process fluctuations Scattering effect Size Optimization
CLC: TN405.97
Type: Master's thesis
Year: 2011
Downloads: 29
Quote: 0
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Abstract


With CMOS integrated circuit technology feature sizes into the nanoscale phase interconnect performance has become the constraints IC design one of the key factors . Nanometer technology , process variations with randomness , the direct result of the the IC physical structure change , thereby affecting interconnect performance , which significantly affect the functionality and performance of integrated circuits . In addition, the integrated circuit manufacturing technology continues to improve , leading to interconnect dimensions continue to decrease, in turn worsened scattering , the scattering effect of the presence will greatly increase the resistivity of the interconnect metal interconnect , thereby affecting such extension when and bandwidth performance. Accordingly, in order to properly analyze and design of integrated circuits, need to consider the impact of process fluctuations and scattering effect on the interconnect performance . Severely affected due to process variations and scattering effect , first of all based on the equivalent Elmore delay model , polynomial chaos theory and the Galerkin method , successive linear approximation method proposed the RCL statistical delay considering process variations model. Then, the problem of scattering effects analysis and specific scattering effect of the interconnect performance . In addition, based on nanoscale technology , interconnect performance on the significant role of the integrated circuit functionality and performance , this paper proposes an optimized interconnect performance interconnect sizing optimization model . Hspice simulation results show that the proposed delay model and interconnect sizing optimization model accuracy are high , and the algorithm is simple and can be applied to the analysis and design of integrated circuits .

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > General issues > Manufacturing process > Interconnection and multi - layer wiring technology
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