|
Radio Frequency Identification (RFID) technology is gradually on the rise with the development and maturity of the communication technology and integrated circuit technology and an automatic identification technology , has been widely used in logistics , retail sales , production management and other fields . As technology continues to evolve , the research and development of RFID technology put forward higher requirements. In this paper, the limitations of RFID tags chip low-cost , low -power , low-cost, low-power baseband controller design study . First, the article describes the sources of the power consumption of CMOS digital integrated circuits , low -power design basic methods and different design stages of low-power design techniques . Secondly, the power consumption of each part of the circuit in the tag chip , a novel low-cost , low-power baseband controller implementation architecture , analysis of the characteristics of the architecture . Then , for the the baseband controller 's design requirements , combined with research of 13.56 MHz radio frequency identification communication protocol standard ISO / IEC 15693 , a detailed study of clock management module , communication synchronization module , protocol processing modules and memory interface module key design technology . Finally, a protocol - compliant baseband controller design , and discuss a comprehensive implementation strategy of the chip , FPGA prototype verification platform , and the final completion of the physical design of the chip . Simulation results show the baseband controller design requirement to comply with the agreement . The baseband controller test chip using SMIC 0.35μm embedded EEPROM process flow sheet , the chip core circuit area is only 0.48 × 0.48 mm2, by using Synopsys' Power Compiler analysis chip consumes only 66.8μW, and with other published the results were compared , this paper designed to achieve a low-cost , low -power design goals .
|