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Design of Digital Communication System Modem

Author: YangShuShu
Tutor: WangJianXin
School: Nanjing University of Technology and Engineering
Course: Communication and Information System
Keywords: RS Code Convolutional Code Interleaving Viterbi Decoding Garnder
CLC: TN915.05
Type: Master's thesis
Year: 2010
Downloads: 141
Quote: 1
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Abstract


This thesis contains the design of a modulator/demodulator in a digital communication system on the DSP platform. Firstly, the overall system design is introduced, and secondly the principle and implementation of channel coding and decoding is addressed. There will be errors for digital signal transmitted in the channel due to thermal noise, fading, interference from human-beings and so on. Error correction technology is employed to decrease the errors thus ensuring the reliability of information transmission. The cascade of RS encoding and decoding and convolution coding and Viterbi decoding is used to realize the channel coding and decoding in this thesis, that is, the outer coding is RS encoding and decoding and the inner coding is convolution encoding and Viterbi decoding. Thirdly, the principle and realization of interleaving and de-interleaving is introduced. Error correcting code is commonly used to correct random errors. However, burst interfere is often encountered in practical communication system. The number of burst errors exceeds the correction capability of the error correcting code because of the un-expectation of the errors as a result of a continuous multiple errors. In order to combat these burst errors using error correcting code, error correcting code is often used together with interleaving technology, interleaver added to the transmitter and de-interleaver added to the receiver, to de-spread the burst errors of channel in the time dimension, and change the burst error channel into independent random error channel thus achieve the goal of correction errors. Finally, timing synchronization is introduced. Sampling can not be achieved at optimal time instant because of the channel propagation delay and the clock skew between sending and receiving, so there exists large difference between the collected data and real data. The receiver clock must be synchronized with the input signal to sample at the optimal sampling time to minimize the bit error rate and the time synchronization method used in this thesis is based on Garnder algorithm.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Communicate > Communication network > General issues > Communication network equipment
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