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Optimized VLIW Compile Technologies for High Density Computing on FT64 Stream Processor

Author: GuanMaoLin
Tutor: ZhangChunYuan
School: National University of Defense Science and Technology
Course: Computer Science and Technology
Keywords: Stream processors FT64 VLIW Compiled load schedule Merging operations
CLC: TP332
Type: Master's thesis
Year: 2007
Downloads: 36
Quote: 0
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Abstract


Flow architecture is emerging in recent years , a high performance architecture . FT64 64 stream processors as the design of the first independent research , its core level using SIMD VLIW execution mode , parallel computational cluster development program distributed register file structure to support large-scale functional unit the array of the need for capacity and speed of the register . The VLIW technology facilitates chip to enhance the frequency , lower power consumption , as well as high demands on the compiler , when the extension of the application areas , the application to register demand increases rapidly making single register file distributed register file capacity become a bottleneck in the application programming and compiler . In this paper, a stream processors , VLIW compiler technology for the FT64 provides efficient VLIW compiler to provide compiler support for the efficient execution of the user program . There are studies on the basis of the based ISCD source code , application background and engineering practice needs to achieve its core-level compiler designed for FT64 stream processors . Background compiler implementation focused on the strategy of choice , engineering and processing bottleneck part . Communication scheduling to ensure efficient VLIW scheduling FT64 core shared interconnect structure ; the load schedule Strategies reduce program performance makes register allocation succeeds avoid the performance loss caused by overload register ; targeted program the features in the use of multiply-and-accumulate operation automatically merge algorithm to improve compiler efficiency . Compiler to achieve in this paper has been in the FT64 stream processor system running into practical use, and have achieved very good results . The performance of the compiler of this article is still FT64 measured and performance analysis results show that , to take a variety of optimization measures , the compiler can well identify the parallelism in the program , and achieved the expected effect.

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Electronic digital computer (not a continuous role in computer ) > Arithmetic unit and the controller (CPU)
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